There is a continued effort to develop semiconductor memories which are less susceptible to both externally and internally generated noise signals. As the cell size of each generation of memory becomes smaller, the voltages representative of the stored digital ones or zeros also become smaller. Hence, the presence of any noise signal coupled into the low level signal lines of a memory can adversely affect the reliability of the memory.
In the well-known core memories employing toroidal magnetic cores as the memory element wherein wires carry the small data signals, electromagnetic interference was reduced by twisting the pairs of bit line wires carrying the incoming and outgoing currents to the magnetic core assembly. In this manner, undesired electrical signals were induced into both wires of the bit line by the same magnitude. With the same amplitude of a noise signal induced into both such wires, a differential-type sense amplifier could easily detect the small analog signal generated when the magnetic core switched states, even when accompanied by the common mode noise.
With the current almost exclusive use of semiconductor memories, the problem presented by induced noise signals is not so easily solved. The problem is even more exacerbated in semiconductor memories where the metal or polysilicon conductor lines are only on the order of a few microns apart. Where such closely adjacent lines carry, for example, five volt logic signals, such signals can be capacitively coupled to other signal lines, such as the bit lines of the memory. Semiconductor memory sense amplifiers have become very sophisticated in attempts to provide a high rejection to noise signals on the bit lines, while at the same time being highly sensitive to memory readout signals.
In a microprocessor chip having bidirectional data and address buses coupled to other circuits on the chip, the possibility of noise interference with the microprocessor memory, which is also located on the chip, increases. In recent microprocessor designs, it is advantageous to fabricate the memory at a subsurface level, with the data or address lines overlying the memory. This is advantageous both from the standpoint of coupling the data bit lines to the memory input, as well as coupling the memory output back to the data lines. Space is also economized. This type of architecture presents a classical opportunity for the inducement of undesired electrical signals from the data or address lines into the bit lines of the memory.
The noise interference problem is compounded in memory designs employing a complementary bit line architecture. In this type of memory, two low level signal bit lines are required per cell for writing data therein, as well as for reading data out of the cell. A high level logic signal transition on an overlying conductor, or on a conductor adjacent the complementary bit lines, can be capacitively coupled in disproportionate amounts into the bit lines. In this event, the differential sense amplifier may be unable to distinguish between induced noise and a valid logic signal read from the memory cell.
It can be seen from the foregoing that a need exists for an improved semiconductor memory structure which reduces the susceptibility of induced noise signals into the memory bit lines. There is an associated need for a complementary bit line structure which reduces the effects of noise signals induced into the bit lines.